Electronic devices and components have found numerous applications in chemistry and biology (more generally, “life sciences”), especially for detection and measurement of various aspects of chemical reactions and substance composition. One such electronic device is referred to as an ion-sensitive field effect transistor, often denoted in the relevant literature as ISFET (or pHFET). ISFETs conventionally have been explored, primarily in the academic and research community, to facilitate measurement of the hydrogen ion concentration of a solution (commonly denoted as “pH”).
More specifically, an ISFET is an impedance transformation device that operates in a manner similar to that of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and is particularly configured to selectively measure ion activity in a solution (e.g., hydrogen ions in the solution are the “analyte”). A detailed theory of operation of an ISFET is given in “Thirty years of ISFETOLOGY: what happened in the past 30 years and what may happen in the next 30 years,” P. Bergveld, Sens. Actuators, 88 (2003), pp. 1-20, which publication is hereby incorporated herein by reference.
FIG. 1 illustrates a cross-section of a p-type (p-channel) ISFET 50 fabricated using a conventional CMOS (Complimentary Metal Oxide Semiconductor) process. P-type ISFET fabrication is based on a p-type silicon substrate 52, in which an n-type well 54 forming a transistor “body” is formed. Highly doped p-type (p+) regions S and D, constituting a source 56 and a drain 58 of the ISFET, are formed within the n-type well 54. A highly doped n-type (n+) region B is also formed within the n-type well to provide a conductive body (or “bulk”) connection 62 to the n-type well. An oxide layer 65 is disposed above the source, drain and body connection regions, through which openings are made to provide electrical connections (via electrical conductors) to these regions; for example, metal contact 66 serves as a conductor to provide an electrical connection to the drain 58, and metal contact 68 serves as a conductor to provide a common connection to the source 56 and n-type well 54, via the highly conductive body connection 62. A polysilicon gate 64 is formed above the oxide layer at a location above a region 60 of the n-type well 54, between the source 56 and the drain 58. Because it is disposed between the polysilicon gate 64 and the transistor body (i.e., the n-type well), the oxide layer 65 often is referred to as the “gate oxide.”
Like a MOSFET, the operation of an ISFET is based on the modulation of charge concentration caused by a MOS (Metal-Oxide-Semiconductor) capacitance constituted by the polysilicon gate 64, the gate oxide 65 and the region 60 of the n-type well 54 between the source and the drain. When a negative voltage is applied across the gate and source regions (VGs<0 Volts), a “p-channel” 63 is created at the interface of the region 60 and the gate oxide 65 by depleting this area of electrons. This p-channel 63 extends between the source and the drain, and electric current is conducted through the p-channel when the gate-source potential VGS is negative enough to attract holes from the source into the channel. The gate-source potential at which the channel 63 begins to conduct current is referred to as the transistor's threshold voltage VTH (the transistor conducts when VGS has an absolute value greater than the threshold voltage VTH). The source is so named because it is the source of the charge carriers (holes for a p-channel) that flow through the channel 63; similarly, the drain is where the charge carriers leave the channel 63.
In the ISFET 50 of FIG. 1, the n-type well 54 (transistor body), via the body connection 62, is forced to be biased at a same potential as the source 56 (i.e., VSB=0 Volts), as seen by the metal contact 68 connected to both the source 56 and the body connection 62. This connection prevents forward biasing of the p+ source region and the n-type well, and thereby facilitates confinement of charge carriers to the area of the region 60 in which the channel 63 may be formed. Any potential difference between the source 56 and the body/n-type well 54 (a non-zero source-to-body voltage VSB) affects the threshold voltage VTH of the ISFET according to a nonlinear relationship, and is commonly referred to as the “body effect,” which in many applications is undesirable.
As also shown in FIG. 1, the polysilicon gate 64 of the ISFET 50 is coupled to multiple metal layers disposed within one or more additional oxide layers 75 disposed above the gate oxide 65 to form a “floating gate” structure 70. The floating gate structure is so named because it is electrically isolated from other conductors associated with the ISFET; namely, it is sandwiched between the gate oxide 65 and a passivation layer 72. In the ISFET 50, the passivation layer 72 constitutes an ion-sensitive membrane that gives rise to the ion-sensitivity of the device; i.e., the presence of ions in an “analyte solution” 74 (a solution containing ions of interest) in contact with the passivation layer 72, particularly in a sensitive area 78 above the floating gate structure 70, alters the electrical characteristics of the ISFET so as to modulate a current flowing through the p-channel 63 between the source 56 and the drain 58. The passivation layer 72 may comprise any one of a variety of different materials to facilitate sensitivity to particular ions; for example, passivation layers comprising silicon nitride or silicon oxynitride generally provide sensitivity to hydrogen ion concentration (pH) in the analyte solution 74, whereas passivation layers comprising polyvinyl chloride containing valinomycin provide sensitivity to potassium ion concentration in the analyte solution (materials suitable for passivation layers and sensitive to other ions such as sodium, silver, iron, bromine, iodine, calcium, and nitrate, for example, are known).
With respect to ion sensitivity, an electric potential difference, commonly referred to as a “surface potential,” arises at the solid/liquid interface of the passivation layer 72 and the analyte solution 74 as a function of the ion concentration in the sensitive area 78 due to a chemical reaction (e.g., usually involving the dissociation of oxide surface groups by the ions in the analyte solution in proximity to the sensitive area 78). This surface potential in turn affects the threshold voltage VTH of the ISFET; thus, it is the threshold voltage VTH of the ISFET that varies with changes in ion concentration in the analyte solution 74 in proximity to the sensitive area 78.
FIG. 2 illustrates an electric circuit representation of the p-channel ISFET 50 shown in FIG. 1. With reference again to FIG. 1, a reference electrode 76 (a conventional Ag/AgCl electrode) in the analyte solution 74 determines the electric potential of the bulk of the analyte solution itself and is analogous to the gate terminal of a conventional MOSFET, as shown in FIG. 2. In a linear or non-saturated operating region of the ISFET, the drain current ID is given as:
                                          I            D                    =                                    β              ⁡                              (                                                      V                    GS                                    -                                      V                    TH                                    -                                                            1                      2                                        ⁢                                          V                      DS                                                                      )                                      ·                          V              DS                                      ,                            (        1        )            
where VDS is the voltage between the drain and the source, and β is a transconductance parameter (in units of Amps/Volts2) given by:
                              β          =                      μ            ⁢                                                  ⁢                                          C                ox                            ⁡                              (                                  W                  L                                )                                                    ,                            (        2        )            
where μ represents the carrier mobility, Cox is the gate oxide capacitance per unit area, and the ratio W/L is the width to length ratio of the channel 63. If the reference electrode 76 provides an electrical reference or ground (VG=0 Volts), and the drain current ID and the drain-to-source voltage VDS are kept constant, variations of the source voltage VS of the ISFET directly track variations of the threshold voltage VTH, according to Eq. (1); this may be observed by rearranging Eq. (1) as:
                              V          S                =                              -                          V              TH                                -                                    (                                                                    I                    D                                                        β                    ⁢                                                                                  ⁢                                          V                      DS                                                                      +                                                      V                    DS                                    2                                            )                        .                                              (        3        )            
Since the threshold voltage VTH of the ISFET is sensitive to ion concentration as discussed above, according to Eq. (3) the source voltage VS provides a signal that is directly related to the ion concentration in the analyte solution 74 in proximity to the sensitive area 78 of the ISFET. In exemplary conventional ISFETs employing a silicon nitride or silicon oxynitride passivation layer 72 for pH-sensitivity, a threshold voltage sensitivities ΔVTH (i.e., a change in threshold voltage with change in pH of the analyte solution) of approximately 30 mV/pH to 50 mV/pH have been observed (with a theoretical maximum sensitivity of 59.2 mV/pH at 298 degrees Kelvin).
Prior research efforts to fabricate ISFETs for pH measurements based on conventional CMOS processing techniques typically have aimed to achieve high signal linearity over a pH range from 1-14. Using an exemplary threshold sensitivity of approximately 50 mV/pH, and considering Eq. (3) above, this requires a linear operating range of approximately 700 mV for the source voltage VS. As discussed above in connection with FIG. 1, the threshold voltage VTH of ISFETs (as well as MOSFETs) is affected by any voltage VSB between the source and the body (n-type well 54). More specifically, the threshold voltage VTH is a nonlinear function of a nonzero source-to-body voltage VSB. Accordingly, so as to avoid compromising linearity due to a difference between the source and body voltage potentials (i.e., to mitigate the “body effect”), as shown in FIG. 1 the source 56 and body connection 62 of the ISFET 50 often are coupled to a common potential via the metal contact 68. This body-source coupling also is shown in the electric circuit representation of the ISFET 50 shown in FIG. 2.
Previous efforts to fabricate two-dimensional arrays of ISFETs based on the ISFET design of FIG. 1 have resulted in a maximum of 256 ISFET sensor elements, or “pixels,” in an array (i.e., a 16 pixel by 16 pixel array). Exemplary research in ISFET array fabrication are reported in the publications “A large transistor-based sensor array chip for direct extracellular imaging,” M. J. Milgrew, M. O. Riehle, and D. R. S. Cumming, Sensors and Actuators, B: Chemical, 111-112, (2005), pp. 347-353, and “The development of scalable sensor arrays using standard CMOS technology,” M. J. Milgrew, P. A. Hammond, and D. R. S. Cumming, Sensors and Actuators, B: Chemical, 103, (2004), pp. 37-42, which publications are incorporated herein by reference and collectively referred to hereafter as “Milgrew et al.” Other research efforts relating to the realization of ISFET arrays are reported in the publications “A very large integrated pH-ISFET sensor array chip compatible with standard CMOS processes,” T. C. W. Yeow, M. R. Haskard, D. E. Mulcahy, H. I. Seo and D. H. Kwon, Sensors and Actuators B: Chemical, 44, (1997), pp. 434-440 and “Fabrication of a two-dimensional pH image sensor using a charge transfer technique,” Hizawa, T., Sawada, K., Takao, H., Ishida, M., Sensors and Actuators, B: Chemical 117 (2), 2006, pp. 509-515, which publications also are incorporated herein by reference.
FIG. 3 illustrates one column 85j of a two-dimensional ISFET array according to the design of Milgrew et al. The column 85j includes sixteen (16) pixels 801 through 8016 and, as discussed further below in connection with FIG. 7, a complete two-dimensional array includes sixteen (16) such columns 85j (j=1, 2, 3, . . . 16) arranged side by side. As shown in FIG. 3, a given column 85j includes a current source ISOURCEj that is shared by all pixels of the column, and ISFET bias/readout circuitry 82j (including current sink ISINKj) that is also shared by all pixels of the column. Each ISFET pixel 801 through 8016 includes a p-channel ISFET 50 having an electrically coupled source and body (as shown in FIGS. 1 and 2), plus two switches S1 and S2 that are responsive to one of sixteen row select signals (RSEL1 through RSEL16, and their complements). As discussed below in connection with FIG. 7, a row select signal and its complement are generated simultaneously to “enable” or select a given pixel of the column 85j, and such signal pairs are generated in some sequence to successively enable different pixels of the column one at a time.
As shown in FIG. 3, the switch S2 of each pixel 80 in the design of Milgrew et al. is implemented as a conventional n-channel MOSFET that couples the current source ISOURCEj to the source of the ISFET 50 upon receipt of the corresponding row select signal. The switch S1 of each pixel 80 is implemented as a transmission gate, i.e., a CMOS pair including an n-channel MOSFET and a p-channel MOSFET, that couples the source of the ISFET 50 to the bias/readout circuitry 82j upon receipt of the corresponding row select signal and its complement. An example of the switch S11 of the pixel 801 is shown in FIG. 4, in which the p-channel MOSFET of the transmission gate is indicated as S1IP and the n-channel MOSFET is indicated as S11N. In the design of Milgrew et al., a transmission gate is employed for the switch S1 of each pixel so that, for an enabled pixel, any ISFET source voltage within the power supply range VDD to VSS may be applied to the bias/readout circuitry 82j and output by the column as the signal VSj. From the foregoing, it should be appreciated that each pixel 80 in the ISFET sensor array design of Milgrew et al. includes four transistors, i.e., a p-channel ISFET, a CMOS-pair transmission gate including an n-channel MOSFET and a p-channel MOSFET for switch S1, and an n-channel MOSFET for switch S2.
As also shown in FIG. 3, the bias/readout circuitry 82j employs a source-drain follower configuration in the form of a Kelvin bridge to maintain a constant drain-source voltage VDSj and isolate the measurement of the source voltage VDSj from the constant drain current ISOURCEj for the ISFET of an enabled pixel in the column 85j. To this end, the bias/readout circuitry 82j includes two operational amplifiers A1 and A2, a current sink ISINKj, and a resistor RSDJ. The voltage developed across the resistor RSDJ due to the current ISINKj flowing through the resistor is forced by the operational amplifiers to appear across the drain and source of the ISFET of an enabled pixel as a constant drain-source voltage VDSj. Thus, with reference again to Eq. (3), due to the constant VDSj and the constant ISOURCEj, the source voltage VSj of the ISFET of the enabled pixel provides a signal corresponding to the ISFETs threshold voltage VTH, and hence a measurement of pH in proximity to the ISFETs sensitive area (see FIG. 1). The wide dynamic range for the source voltage VSj provided by the transmission gate S1 ensures that a full range of pH values from 1-14 may be measured, and the source-body connection of each ISFET ensures sufficient linearity of the ISFETs threshold voltage over the full pH measurement range.
In the column design of Milgrew et al. shown in FIG. 3, it should be appreciated that for the Kelvin bridge configuration of the column bias/readout circuitry 82j to function properly, a p-channel ISFET 50 as shown in FIG. 1 must be employed in each pixel; more specifically, an alternative implementation based on the Kelvin bridge configuration is not possible using an n-channel ISFET. With reference again to FIG. 1, for an n-channel ISFET based on a conventional CMOS process, the n-type well 54 would not be required, and highly doped n-type regions for the drain and source would be formed directly in the p-type silicon substrate 52 (which would constitute the transistor body). For n-channel FET devices, the transistor body typically is coupled to electrical ground. Given the requirement that the source and body of an ISFET in the design of Milgrew et al. are electrically coupled together to mitigate nonlinear performance due to the body effect, this would result in the source of an n-channel ISFET also being connected to electrical ground (i.e., VS=VB=0 Volts), thereby precluding any useful output signal from an enabled pixel. Accordingly, the column design of Milgrew et al. shown in FIG. 3 requires p-channel ISFETs for proper operation.
It should also be appreciated that in the column design of Milgrew et al. shown in FIG. 3, the two n-channel MOSFETs required to implement the switches S1 and S2 in each pixel cannot be formed in the n-type well 54 shown in FIG. 1, in which the p-channel ISFET for the pixel is formed; rather, the n-channel MOSFETs are formed directly in the p-type silicon substrate 52, beyond the confines of the n-type well 54 for the ISFET. FIG. 5 is a diagram similar to FIG. 1, illustrating a wider cross-section of a portion of the p-type silicon substrate 52 corresponding to one pixel 80 of the column 85j shown in FIG. 3, in which the n-type well 54 containing the drain 58, source 56 and body connection 62 of the ISFET 50 is shown alongside a first n-channel MOSFET corresponding to the switch S2 and a second n-channel MOSFET S11N constituting one of the two transistors of the transmission gate S11 shown in FIG. 4.
Furthermore, in the design of Milgrew et al., the p-channel MOSFET required to implement the transmission gate S1 in each pixel (e.g., see S1Ip in FIG. 4) cannot be formed in the same n-type well in which the p-channel ISFET 50 for the pixel is formed. In particular, because the body and source of the p-channel ISFET are electrically coupled together, implementing the p-channel MOSFET S11p in the same n-well as the p-channel ISFET 50 would lead to unpredictable operation of the transmission gate, or preclude operation entirely. Accordingly, two separate n-type wells are required to implement each pixel in the design of Milgrew et al. FIG. 6 is a diagram similar to FIG. 5, showing a cross-section of another portion of the p-type silicon substrate 52 corresponding to one pixel 80, in which the n-type well 54 corresponding to the ISFET 50 is shown alongside a second n-type well 55 in which is formed the p-channel MOSFET S11p constituting one of the two transistors of the transmission gate S11 shown in FIG. 4. It should be appreciated that the drawings in FIGS. 5 and 6 are not to scale and may not exactly represent the actual layout of a particular pixel in the design of Milgrew et al.; rather these figures are conceptual in nature and are provided primarily to illustrate the requirements of multiple n-wells, and separate n-channel MOSFETs fabricated outside of the n-wells, in the design of Milgrew et al.
The array design of Milgrew et al. was implemented using a 0.35 micrometer (μm) conventional CMOS fabrication process. In this process, various design rules dictate minimum separation distances between features. For example, according to the 0.35 μm CMOS design rules, with reference to FIG. 6, a distance “a” between neighboring n-wells must be at least three (3) micrometers. A distance “a/2” also is indicated in FIG. 6 to the left of the n-well 54 and to the right of the n-well 55 to indicate the minimum distance required to separate the pixel 80 shown in FIG. 6 from neighboring pixels in other columns to the left and right, respectively. Additionally, according to the 0.35 μm CMOS design rules, a distance “b” shown in FIG. 6 representing the width in cross-section of the n-type well 54 and a distance “c” representing the width in cross-section of the n-type well 55 are each on the order of approximately 3 μm to 4 μm (within the n-type well, an allowance of 1.2 μm is made between the edge of the n-well and each of the source and drain, and the source and drain themselves have a width on the order of 0.7 μm). Accordingly, a total distance “d” shown in FIG. 6 representing the width of the pixel 80 in cross-section is on the order of approximately 12 μm to 14 μm. In one implementation, Milgrew et al. report an array based on the column/pixel design shown in FIG. 3 comprising geometrically square pixels each having a dimension of 12.8 μm by 12.8 μm.
In sum, the ISFET pixel design of Milgrew et al. is aimed at ensuring accurate hydrogen ion concentration measurements over a pH range of 1-14. To ensure measurement linearity, the source and body of each pixel's ISFET are electrically coupled together. To ensure a full range of pH measurements, a transmission gate 51 is employed in each pixel to transmit the source voltage of an enabled pixel. Thus, each pixel of Milgrew's array requires four transistors (p-channel ISFET, p-channel MOSFET, and two n-channel MOSFETs) and two separate n-wells (FIG. 6). Based on a 0.35 micrometer conventional CMOS fabrication process and the corresponding design rules, the pixels of such an array have a minimum size appreciably greater than 10 μm, i.e., on the order of approximately 12 μm to 14 μm.
FIG. 7 illustrates a complete two-dimensional pixel array 95 according to the design of Milgrew et al., together with accompanying row and column decoder circuitry and measurement readout circuitry. The array 95 includes sixteen columns 851 through 8516 of pixels, each column having sixteen pixels as discussed above in connection with FIG. 3 (i.e., a 16 pixel by 16 pixel array). A row decoder 92 provides sixteen pairs of complementary row select signals, wherein each pair of row select signals simultaneously enables one pixel in each column 851 through 8516 to provide a set of column output signals from the array 95 based on the respective source voltages VS1 through VS16 of the enabled row of ISFETs. The row decoder 92 is implemented as a conventional four-to-sixteen decoder (i.e., a four-bit binary input ROW1-ROW4 to select one of 24 outputs). The set of column output signals VS1 through VS16 for an enabled row of the array is applied to switching logic 96, which includes sixteen transmission gates S1 through S16 (one transmission gate for each output signal). As above, each transmission gate of the switching logic 96 is implemented using a p-channel MOSFET and an n-channel MOSFET to ensure a sufficient dynamic range for each of the output signals VS1 through VS16. The column decoder 94, like the row decoder 92, is implemented as a conventional four-to-sixteen decoder and is controlled via the four-bit binary input COL1-COL4 to enable one of the transmission gates S1 through S16 of the switching logic 96 at any given time, so as to provide a single output signal VS from the switching logic 96. This output signal VS is applied to a 10-bit analog to digital converter (ADC) 98 to provide a digital representation D1-D10 of the output signal VS corresponding to a given pixel of the array.
As noted earlier, individual ISFETs and arrays of ISFETs similar to those discussed above have been employed as sensing devices in a variety of applications involving chemistry and biology. In particular, ISFETs have been employed as pH sensors in various processes involving nucleic acids such as DNA. Some examples of employing ISFETs in various life-science related applications are given in the following publications, each of which is incorporated herein by reference: Massimo Barbaro, Annalisa Bonfiglio, Luigi Raffo, Andrea Alessandrini, Paolo Facci and Imrich Barak, “Fully electronic DNA hybridization detection by a standard CMOS biochip,” Sensors and Actuators B: Chemical, Volume 118, Issues 1-2, 2006, pp. 41-46; Toshinari Sakurai and Yuzuru Husimi, “Real-time monitoring of DNA polymerase reactions by a micro ISFET pH sensor,” Anal. Chem., 64(17), 1992, pp 1996-1997; S. Purushothaman, C. Toumazou, J. Georgiou, “Towards fast solid state DNA sequencing,” Circuits and Systems, vol. 4, 2002, pp. IV-169 to IV-172; S. Purushothaman, C. Toumazou, C. P. Ou, “Protons and single nucleotide polymorphism detection: A simple use for the Ion Sensitive Field Effect Transistor,” Sensors and Actuators B: Chemical, Vol. 114, no. 2, 2006, pp. 964-968; A. L. Simonian, A. W. Flounders, J. R. Wild, “FET-Based Biosensors for The Direct Detection of Organophosphate Neurotoxins,” Electroanalysis, Vol. 16, No. 22, 2004, pp. 1896-1906; C. Toumazou, S. Purushothaman, “Sensing Apparatus and Method,” United States Patent Application 2004-0134798, published Jul. 15, 2004; and T. W. Koo, S. Chan, X. Su, Z. Jingwu, M. Yamakawa, V. M. Dubin, “Sensor Arrays and Nucleic Acid Sequencing Applications,” United States Patent Application 2006-0199193, published Sep. 7, 2006.
In general, the development of rapid and sensitive nucleic acid sequencing methods utilizing automated DNA sequencers has significantly advanced the understanding of biology. The term “sequencing” refers to the determination of a primary structure (or primary sequence) of an unbranched biopolymer, which results in a symbolic linear depiction known as a “sequence” that succinctly summarizes much of the atomic-level structure of the sequenced molecule. “DNA sequencing” particularly refers to the process of determining the nucleotide order of a given DNA fragment. Analysis of entire genomes of viruses, bacteria, fungi, animals and plants is now possible, but such analysis generally is limited due to the cost and throughput of sequencing. More specifically, present conventional sequencing methods are limited in terms of the accuracy of the sequence, the length of individual templates that can be sequenced, the cost of the sequence, and the rate of sequence determination.
Despite improvements in sample preparation and sequencing technologies, none of the present conventional sequencing strategies, including those to date that may involve ISFETs, has provided the cost reductions required to increase throughput to levels required for analysis of large numbers of individual human genomes. It is necessary to sequence a large number of individual genomes to understand the genetic basis of disease and aging. In addition, a large number of cancers will need to be sequenced to understand the somatic changes underlying cancer. Some recent efforts have made significant gains in both the ability to prepare genomes for sequencing and to sequence large numbers of templates simultaneously. However, these and other efforts are still limited by the relatively large size of the reaction volumes needed to prepare templates that are detectable by these systems, as well as the need for special nucleotide analogues, and complex enzymatic or fluorescent methods to read out the bases.